As known multiplier structures or multiplication functions are being used extensively in digital circuits, for example for processors, digital signal processors (DSP) or graphic chip sets etc. An error in a chip with a multiplication function can entail—as also errors in other circuit structures—failure of the entire chip.
Therefore maximum importance is attached to the verification of digital circuits, after these have been developed computer-aided by means of a synthesis tool, for example. Recently, in this connection so-called equivalence testing has gained more and more significance. In this case, it is checked to what extent the functions implemented in the digital circuit are equivalent or otherwise with the circuit structures, described by a reference description, for example an RTL—(“register transfer level”), VHDL—(“very high speed IC HW description language”) or Verilog-description with regard to their operating mode. Modern equivalence checkers can process digital circuits with several million gates. In this case, the equivalence checkers deliver very good results particularly, if the circuit designs to be compared with one another, that is to say the digital circuit to be verified and the reference circuit description on which it is based, have a good degree of structural similarity. On the other hand, an equivalence test does not deliver satisfactory results, if the digital circuit to be verified and the reference description on which it is based structurally differ substantially to a greater or lesser degree and therefore only have few internal equivalences.
In this case the formal verification of multiplier structures and/or multiplication functions is considered one of the most difficult problems with regard to the equivalence checking of digital circuits.
It is known that decimal numbers A and B can be multiplied together in various ways. Thus, for example, either the product A×B can be formed or the product B×A. In the known way the product can also be formed by the individual digits of the two decimal numbers being multiplied together and the sum of the sub-products resulting therefrom then being formed. The sequence, in which the sub-products are added up, can vary for each individual case, naturally without another result of multiplying the numbers A and B being obtained. Dependent on what method is selected for multiplying the numbers A and B, in order to implement the corresponding multiplier structure one of different possible implementation alternatives or implementation variants can be employed, whereby although all these different implementation variants deliver the same multiplication result, with regard to their structure possibly they have no or only few internal equivalences. Furthermore, naturally also various architectures can be used for the implementation of multiplier structures.
As an added difficulty it is also a fact that multiplication functions in digital circuits usually do not appear in isolation, but are embedded in environment logic. At the same time in certain circumstances it is to be considered that the limits of the multiplication functions—due to circuit optimizations for example—are only incompletely given (“sea of gates”) and therefore under formal criteria the multiplication functions in certain circumstances are no longer (explicitly) present.
Until now no process has been known with which multiplier structures within digital circuits can be reliably and quickly recognized. Due to the functional optimization possibilities of modern synthesis processes when designing digital circuits for example, simple “pattern matching” methods, which simply concern comparison of the circuit structure with a reference circuit structure, are ruled out for example. With regard to the verification of multiplier structures various competing methods are known.
The simplest procedure, which may be designated as generic method, proposes not allowing the multiplier structures contained in a digital circuit to undergo any kind of special treatment, so that before verification of the digital circuit in the form of an equivalence test no explicit recognition of the multiplier structures or multiplication functions contained in the digital circuit is necessary. The disadvantage connected with this procedure however is that the equivalence test frequently needs long run times and possibly may end in failure of the verification. The run time requirement of the equivalence test heavily depends on (random) selection of the implementation alternative for the individual multiplier structures, on which the equivalence test is based.
In accordance with a further method for the verification of multiplier structures before executing the equivalence test for each individual multiplier structure or multiplication function, the physically selected implementation alternative is defined, that is to say specified by the user. The problem connected with this method however is that this knowledge is frequently not (no longer) available at the time of the verification. If wrong data are given by the user before executing the equivalence test and therefore wrong implementation alternatives are used as the basis of the equivalence test, this method has the same disadvantages as the generic verification process mentioned above.
Finally, various verification processes are also known from the prior art, which are limited to individual multiplication functions or multiplier structures seen in isolation, that is to say the implementation of the digital circuit to be verified as well as the reference description to be compared therewith are only constituted by the multiplication itself. Therefore it is known for example from “Induction-based Gate Level Verification of Multipliers”, Y. T. Chang and K. T. Cheng, International Conference on Computer Aided Design (ICCAD), page 190 et seq., 2001, using an induction-based method to split up the verification of n-bit multipliers into n sub-equivalence checks. “Equivalence Checking of Integer Multipliers”, J.-C. Chen and Y-A. Chen, Asian Pacific Design Automation Conference (ASPDAC), 2001 for example proposes the depiction of n×n array multipliers or n×n Wallace Baum multipliers over so-called “Multiplicative Power Hybrid Decision Diagrams” (*PHDD) in the form of an illustration on data element level in order to test the equivalence of two integral multipliers. In addition, the depiction of integral multipliers on bit level in the form of so-called “Binary Decision Diagrams” (BDD), or on data element level in the form of so-called “Multiplicative Binary Moment Diagrams” (*BMD) is disclosed in this publication. Finally “Verification of Integer Multipliers on the Arithmetic Bit Level”, D. Stoffel and W. Kunz, International Conference on Computer-Aided Design (ICCAD), P. 183-189, 2001, for the verification of integral multipliers proposes the use of a Boolean mapping or image algorithm, which extracts a network of half-adders from a gate netlist of an adder circuit, in order subsequently by means of simple arithmetical operations to be able to carry out an equivalence test in the case of known arithmetic depiction on bit level of the adder circuit. The method proposed in this publication is based on the realization, already described above, that integral multiplications can be essentially divided into two sections, that is to say on the one hand formation of sub-products and on the other hand addition of the sub-products for the final multiplication result.
As previously mentioned the verification processes described last are limited to individual, isolated multiplication functions in each case. These verification processes however in practice are ruled out for the verification of digital circuits, that is to say, of synthesis results, since the multiplication functions are usually not present in isolation.
From the prior art therefore no practical processes for the verification of multiplier structures or multiplication functions implemented in digital circuits are known. The efficiency of the verification processes known from the prior art usually heavily depends on the physical implementation of the respective multiplication function. According to the prior art therefore additional information about the type and structure of the multiplier structures in the digital circuit to be verified is indispensable for efficient verification.